A multi-port memory cell provides independent data channels or ports that enable a read or a write operation on each port to addresses asynchronously from each other. For illustration, one port, such as a port P_A, is write accessed while the other port, such as a port P_B, is dummy read accessed. A dummy read refers to a scenario, in which the memory cell is not read accessed, but various signals cause the memory cell to be in a read-like condition and the data for reading is not reliable. Generally, the dummy read from port P_B increases a load on a storage node of the memory cell to be written, and thus prolongs the write time from port P_A. Stated differently, the write operation from port P_A is write disturbed by the dummy read from port P_B. In various approaches, the write disturb is detected based on circuitry that uses a match address of port P_A and port P_B.